Display device

ABSTRACT

An object of the present invention is to suppress occurrence of vertical streaks and ghosts by realizing complete non-overlap sampling in execution of horizontal driving by a clock drive method.  
     A horizontal driving circuit ( 17 ) has a shift register capable of performing a shift operation synchronously with a first clock signal HCK and outputting shift pulses sequentially from respective shift stages thereof; a first switch group for extracting a second clock signal DCK in response to the shift pulses; and a second switch group for sequentially sampling an input video signal in response to the second clock signal DCK extracted by the switches of the first switch group, and supplying the sampled signal to each signal line ( 12 ). An external clock generating circuit ( 18 ) is provided outside a panel ( 33 ) and supplies the second clock signal DCK externally. Further an internal clock generating circuit ( 19 ) is formed in the panel ( 33 ) and supplies the first clock signal HCK to the horizontal driving circuit ( 17 ) in accordance with the second clock signal DCK.

TECHNICAL FIELD

The present invention relates to a display device, and more particularlyto an active matrix type display device based on a dot sequentialdriving system adopting a clock drive method in its horizontal drivingcircuit. The invention further relates to a dot sequential driving typeactive matrix display device where a clock drive method is applied toits horizontal driving circuit of a divided sample-and-hold system.

BACKGROUND ART

In a display device such as, for example, an active matrix type liquidcrystal display device using liquid crystal cells as pixel displayelements (electro-optical elements), there is known a dot sequentialdriving type horizontal driving circuit of a structure employing, e.g.,a clock drive method. FIG. 19 shows a conventional example of such ahorizontal driving circuit based on the clock drive method. In thestructure of FIG. 19, the horizontal driving circuit 100 includes ashift register 101, a clock extracting switch group 102, and a samplingswitch group 103.

The shift register 101 is composed of n shift stages (transfer stages)and, in response to an input horizontal start pulse HST, performs ashift operation synchronously with horizontal clock signals HCK and HCKXof mutually opposite phases. Consequently, from the respective shiftstages of the shift register 101, there are sequentially outputted shiftpulses Vs1 to Vsn of which pulse widths are equal to the respectiveperiods of the horizontal clock signals HCK and HCKX, as shown in atiming chart of FIG. 20. These shift pulses Vs1 to Vsn are suppliedrespectively to switches 102-1 to 102-n of the clock extracting switchgroup 102.

The switches 102-1 to 102-n of the clock extracting switch group 102 areconnected, each at one end thereof, alternately to clock lines 104-1 and104-2, which input the horizontal clock signals HCKX and HCKrespectively. In response to shift pulses Vs1 to Vsn delivered from therespective shift stages of the shift register 101, the switches 102-1 to102-n are turned on sequentially to thereby extract the horizontal clocksignals HCKX and HCK in sequence. The clock pulses thus extracted aresupplied as sampling pulses Vh1 to Vhn to switches 103-1 to 103-n of thesampling switch group 103 respectively.

The switches 103-1 to 103-n of the sampling switch group 103 areconnected, each at one end thereof, to a video line 105 for transmissionof a video signal Video therethrough. In response to the sampling pulsesVh1 to Vhn extracted and delivered sequentially via the switches 102-1to 102-n of the clock extracting switch group 102, the switches 103-1 to103-n are turned on sequentially to thereby sample the video signalVideo and then supplies the sampled signal to signal lines 106-1 to106-n of a pixel array (not shown).

In the horizontal driving circuit 100 of the clock drive system in theconventional example mentioned above, the pulses are somewhat delayeddue to the wiring resistance, parasitic capacitance, and so forth in theprocess of transmission from extraction of the horizontal clock signalsHCKX and HCK via the switches 102-1 to 102-n of the clock extractingswitch group 102 to delivery of such extracted signals as samplingpulses Vh1 to Vhn to the respective switches 103-1 to 103-n of thesampling switch group 103.

Such delay of the pulses caused in the process of transmission roundsthe waveforms of the sampling pulses Vh1 to Vhn. Consequently, withregard to the second-stage sampling pulse Vh2 for example, there occursa waveform overlap, as obvious particularly from a timing chart of FIG.21, between the second-stage sampling pulse Vh2 and each of thepreceding first-stage sampling pulse Vh1 and the following third-stagesampling pulse Vh3.

Generally, at the moment when each of the switches 103-1 to 103-n of thesampling switch group 103 is turned on, a charge/discharge noise issuperposed on the video line 105, as shown in FIG. 21, due to therelationship of the potential to the signal lines 106-1 to 106-n.

Under such circumstances, if there exists an overlap between thesampling pulse Vh2 and the pulse of the preceding or following stage asdescribed, the charge/discharge noise derived from turn-on of thethird-stage sampling switch 103-3 is sampled at the second-stagesampling timing based on the sampling pulse Vh2. The sampling switches103-1 to 103-n sample and hold the potential of the video line 105 atthe timing when the sampling pulses Vh1 to Vhn are turned to an “L”level.

At this time, the charge-discharge noises superposed on the video line105 are varied, and the timings of turning the sampling pulses Vh1 toVhn to an “L” level are also varied, so that the sample potentialsobtained through the sampling switches 103-1 to 103-n are consequentlyvaried. As a result, such variations of the sample potentials appear tobe vertical streaks on the display screen to eventually deteriorate theimage quality.

Meanwhile in an active matrix type liquid crystal display device of thedot sequential driving system, as the number of horizontal pixels inparticular increases with advance of attaining a higher definition, itbecomes difficult to ensure a sufficient sampling time to sequentiallysample, in regard to the entire pixels, the input video signal Video ofone route within a limited horizontal effective interval. Therefore, inorder to ensure a sufficient sampling time, there is adopted a methodwhereby, as shown in FIG. 22, the video signal is inputted in parallelthrough m routes (where m is an integer greater than two), while msampling switches are provided for m horizontal pixels as a unit, andthe m pixels as a unit are written sequentially by driving the msampling switches simultaneously in response to one sampling pulse.

There is considered now one case of displaying a thin black line of awidth less than the number m of unit pixels. When such a black line isto be displayed, the video signal Video is inputted with a waveform ofFIG. 23(A) wherein the black level portion thereof is shaped like apulse, and the pulse width thereof is equal to the pulse width of thesampling pulse (B). It is ideal that this pulse-shaped video signalVideo has a rectangular waveform, but due to the wiring resistance,parasitic capacitance, and so forth in the video line for transmissionof the video signal Video, the leading and trailing edges of the pulsewaveform are somewhat rounded (video signal Video′) as shown in FIG.23(C).

If the pulse-shaped video signal Video′ having such rounded leading andtrailing edges is sampled and held in response to the sampling pulsesVh1 to Vhn, there arises an error that, regarding the pulse-shaped videosignal Video′, which is essentially to be sampled and held by thekth-stage sampling pulse Vhk, the leading edge thereof is actuallysampled and held by the preceding-stage sampling pulse Vhk−1, or thetrailing edge of the video signal Video′ is sampled and held by thefollow-stage sampling pulse Vhk+1. As a result, a ghost is generated.Here, a ghost signifies an undesired disturbing image caused induplicate with a deviation from the normal image.

The phase relationship of the video signal Video′ (hereinafter referredto simply as video signal Video) to the sampling pulse Vhk can bechanged in six steps of, e.g., S/H=0 to 5, as shown in FIG. 24, byadjusting the sample-and-hold position on the time base of the videosignal Video in a circuit, which processes the video signal Video.

Now a description will be given on the ghost occurrence dependencyrelative to the sample-and-hold operation. First, there is considered astate where S/H=1. FIG. 25 shows the phase relationship between thevideo signal Video and the sampling pulses Vhk−1, Vhk, and Vhk+1 whenS/H=1 and also shows the potential changes on the signal line. WhenS/H=1, the pulse-shaped video signal Video is sampled and held by thesampling pulse Vhk, so that a black signal is written in the signal lineof the kth stage and a black line is displayed.

However, simultaneously therewith, the black signal is written also inthe signal line of the k−1th stage since the black signal portion (pulseportion) of the video signal Video overlaps with the sampling pulseVhk−1 of the k−1th stage. Consequently, as shown in FIG. 26, a foreghost is caused at a position of the k−1th stage, i.e., anterior in thehorizontal scanning direction. Similarly, when S/H=0, the black signalportion of the video signal Video overlaps with the sampling pulse Vhk−1of the k−1th stage, so that a fore ghost is caused at an anteriorposition in the horizontal scanning direction.

Next, there is considered another state where S/H=5. FIG. 27 shows thephase relationship between the video signal Video and the samplingpulses Vhk−1, Vhk, and Vhk+1 when S/H=5 and also shows the potentialchanges on the signal line. In the case of S/H=5, the video black signaloverlaps with the sampling pulse Vhk+1 of the k+1th stage. The blacksignal is written in the signal line of the k+1th stage when thesampling switch is turned on, and then the potential level is lowered toreturn to the gray level. However, since the amount of overlap is great,the signal line potential fails to return completely down to the graylevel. Therefore, as shown in FIG. 28, a back ghost is caused at aposition of the k+1th stage, i.e., posterior in the horizontal scanningdirection.

In any other case of S/H=1 to 4, as in the above-described case ofS/H=5, the video black signal overlaps with the sampling pulse Vhk+1 ofthe k+1th stage, and the black signal is written in the signal line whenthe sampling switch is turned on. However, since the amount of overlapis smaller and the written black level is lower in comparison with theabove case of S/H=5, the signal line potential returns completely downto the gray level. Consequently, no ghost is caused.

In the process mentioned, a ghost is derived from the overlap betweenthe video signal Video and the sampling pulse. Here, the number ofsample-and-hold positions, where no ghost is caused at any of anteriorand posterior positions as in S/H=2, 3, 4, is defined as a margin to aghost (hereinafter referred to as ghost margin).

Thus, it is impossible to eliminate the problem that the waveform of thepulse-shaped video signal Video are rounded at its leading and trailingedges due to the wiring resistance, parasitic capacitance, and so forthexisting in the video line, but occurrence of a ghost can be avoided byproperly setting an optimal sample-and-hold position in the circuit,which processes the video signal Video.

However, since the waveform of the pulse-shaped video signal Video isrounded at its leading and trailing edges by the wiring resistance,parasitic capacitance and so forth in the video line, the pulse waveformportion of the video signal Video is distorted to overlap with thesampling pulse in the preceding or following stage, so that it isrendered impossible to attain a large ghost margin correspondinglythereto. In the example mentioned above, the ghost margin is limited tothree, i.e., S/H=2, 3, 4.

Next, a description will be given on a conventional active matrix typedisplay device based on a dot sequential driving system where a clockdrive method is applied to its horizontal driving circuit of a dividedsample-and-hold system. The conventional active matrix type displaydevice is composed of a panel having gate lines in rows, signal lines incolumns, and pixels arrayed to form a matrix in the intersections ofsuch rows and columns. Each of the pixels includes, e.g., a thin filmtransistor (TFT) as an active element. There are further provided avertical driving circuit and a horizontal driving circuit. The verticaldriving circuit is connected to each of the gate lines and selects therow of the pixels sequentially. The horizontal driving circuit isconnected to each of the signal lines and writes the video signal in thepixels of the selected row. In the dot sequential driving system, thevideo signal is written dot-sequentially in the pixels of the selectedrow.

In the active matrix type display device, there exists a parasiticcapacitance between a source/drain electrode of the TFT and each of thesignal lines. Some image fault including vertical streaks and so forthmay occur when a potential variation derived from such parasiticcapacitance at the time of writing the video signal via one signal linehas plunged into the adjacent signal line. This vertical streak faultbecomes conspicuous particularly when a checkered pattern is displayedby a line inverse driving system. Alternatively, a vertical streak isliable to occur when a horizontal line having a thickness of one dot(one pixel) is displayed by the line inverse driving system.

In order to prevent such plunge of a video signal between signal lines,there is proposed a divided sample-and-hold driving method, which isdisclosed in Japanese Patent Laid-open No. 2000-267616 for example.According to this divided sample-and-hold method, an input video signalis separated into two routes, and at the time of writing the videosignal by the dot sequential system, the signals of the two routes arewritten while being overlapped with each other in mutually adjacentpixels.

FIG. 29 typically shows an example of a display device adopting theabove divided sample-and-hold driving method. As shown in the diagram,the display device is composed of a panel having gate lines 113 in rows,signal lines 112 in columns, pixels 111 arrayed to form a matrix in theintersections of such rows and columns, and two video lines 125 and 126for supplying video signals Video1 and Video2 separated into two routesin a predetermined phase relationship. Further, a sampling switch group123 is disposed correspondingly to each signal line 112, and two signallines are connected as a unit between the two video lines respectively.More specifically, the first signal line is connected to one video line125 via the sampling switch, and the second signal line is connected tothe other signal line 126 via the sampling switch. Thereafter, the thirdand subsequent signal lines are also connected alternately to the twovideo lines 125 and 126 via the sampling switches. The panel furtherincludes a vertical driving circuit 116 and a horizontal driving circuit117 provided therein. The vertical driving circuit 116 is connected toeach gate line 113 and selects the rows of the pixels 111 sequentially.In other words, the pixels 111 arrayed to form a matrix are selected rowby row sequentially. The horizontal driving circuit 117 operates inaccordance with a clock signal of a predetermined period andsequentially generates sampling pulses A, B, C, D, . . . , which are notoverlapped with respect to the switches of the sampling switch group 123connected to the same video line but are overlapped with respect to theadjacent switches, hence turning on or off the switches in sequence tothereby write the video signal dot-sequentially in the pixels 111 of theselected row. The display device further has a clock generating circuit189 to supply a clock signal HCK, which serves as an a reference to theoperation of the horizontal driving circuit 117, and also supplies astart pulse HST. The horizontal driving circuit 117 is composed of shiftregisters (S/R) 121 connected in a multiplicity of stages and transfersHST in response to HCK sequentially to thereby generate theabove-described sampling pulses A, B, C, D, and so forth.

Referring now to a waveform chart of FIG. 30, a brief explanation willbe given on the operation of the conventional display device shown inFIG. 29. As described, the horizontal driving circuit operates inaccordance with a clock signal HCK and transfers a start pulse HSTsequentially to thereby generate sampling pulses A, B, C, D, and soforth. As obvious from this waveform chart, the sampling pulses overlapwith each other between the mutually adjacent signal lines. That is, thesampling pulse A corresponding to the first signal line overlaps withthe sampling pulse B corresponding to the second signal line. Similarly,the sampling pulse B corresponding to the second signal line overlapswith the sampling pulse C corresponding to the third signal line. Sincethe video signal is supplied from separate video lines to the mutuallyadjacent signal lines, no problem arises from such overlap. Samplingpulses are generated in such a manner as to overlap with respect to thesampling switches of the mutually adjacent signal lines, so that itbecomes possible to prevent the vertical streak fault that has beenknown heretofore. More specifically, a parasitic capacitance is existentbetween the source/drain electrode of each pixel transistor and each ofthe signal lines, and if a potential variation on one signal lineplunges into the adjacent signal line via such parasitic capacitance, noharmful effect is exerted by such plunge of the video signal as therelevant signal line is kept at a low impedance due to the overlapsampling.

In the shown example, a signal potential Sig1 is sampled and held, inresponse to the sampling pulse A, on the corresponding first signalline. Subsequently, a signal potential Sig2 is sampled and held, inresponse to the sampling pulse B, on the second signal line. At thistime, a potential change is produced on the second signal line. Althoughthis potential change plunges also into the first signal line because ofthe parasitic capacitance, the first signal line is kept at a lowimpedance since the corresponding sampling switch is still open at thistime, so that no harmful effect is exerted despite such plunge of thesignal.

FIG. 31 typically represents the video signal sampling timing to eachsignal line and the potential change produced on each video line.Fundamentally, each sampling pulse is so generated as not to overlapwith respect to the sampling switches connected to the same video line.For example, the first signal line and the third signal line areconnected to the same video line. Therefore, the circuit is so designedthat, in principle, the sampling pulse A and the sampling pulse C do notoverlap with each other. Actually, however, some delay is derived fromthe wiring resistance, parasitic capacitance, and so forth in theprocess of transmitting the pulses, hence rounding the waveform. As aresult, a partial overlap is caused between the sampling pulse A and thesampling pulse C. When the sampling pulse C rises in such a state, thecorresponding sampling switch is opened and a charge/discharge isgenerated to the signal line, whereby a potential fluctuation isproduced in the video signal Video1 on the video line, as indicated by asolid-line arrow. At this moment, since the preceding sampling pulse Ahas not yet fallen completely, the potential fluctuation(charge/discharge noise) on the video line is picked up, as indicated bya dotted-line arrow. Consequently, a potential variation sampled on thesignal line is caused to appear as a vertical streak on the screen,hence deteriorating the image quality eventually. Furthermore, becauseof such interference of the video signal between the signal linesconnected to the same video line, there may occur a ghost or the like onthe screen.

DISCLOSURE OF INVENTION

The present invention has been accomplished in view of the problemsmentioned above. It is a first object of the invention to provide adisplay device, which is capable of realizing complete non-overlapsampling in execution of horizontal driving by a clock drive system soas to suppress occurrence of vertical streaks derived from overlapsampling, and further capable of setting a great ghost margin.

A second object of the present invention resides in providingimprovements in an active matrix type display device where a dividedsample-and-hold method is adopted. The display device is capable ofeliminating interference of a video signal caused between signal linesconnected to the same video line, thereby suppressing any image faultinclusive of vertical streaks, ghosts, and the like.

In order to achieve the first object of the present invention mentionedabove, the following means have been contrived. The display device ofthe invention includes a panel having gate lines in rows, signal linesin columns, and pixels arrayed to form a matrix in the intersections ofsuch rows and columns; a vertical driving circuit connected to the gatelines and selecting the row of the pixels sequentially; a horizontaldriving circuit connected to the signal lines and, in response to aclock signal of a predetermined period, writing a video signalsequentially in the pixels of the selected row; and a clock generatingmeans for generating a first clock signal used as a reference to theoperation of the horizontal driving circuit, and also generating asecond clock signal equal in period to but smaller in duty ratio thanthe first clock signal. The horizontal driving circuit has a shiftregister for outputting shift pulses sequentially from respective shiftstages thereof by performing a shift operation synchronously with thefirst clock signal; a first switch group for extracting the second clocksignal in response to the shift pulses outputted sequentially from theshift register; and a second switch group for sampling the input videosignal sequentially in response to the second clock signal extracted bythe switches of the first switch group, and supplying the sampled signalto each signal line. The clock generating means is divided into anexternal clock generating circuit disposed outside the panel andsupplying the second clock signal externally, and an internal clockgenerating circuit formed within the panel and supplying the first clocksignal to the horizontal driving circuit in accordance with the secondclock signal.

More specifically, the internal clock generating circuit includes a Dtype flip-flop for generating the first clock signal by processing thesecond clock signal supplied thereto from the external clock generatingcircuit. In this case, the D type flip-flop is composed of a pluralityof NAND elements. On the other hand, the external clock generatingcircuit is capable of variably adjusting the duty ratio of the secondclock signal.

In the above structure, each switch of the first switch groupsequentially extracts the second clock signal in response to the shiftpulses outputted in sequence from the shift register synchronously withthe first clock signal. As a result, the second clock signal beingsmaller in duty ratio than the first clock signal is supplied as asampling signal to the second switch group. Then each switch of thesecond switch group sequentially samples and holds the input videosignal in response to the sampling signal and supplies the video signalto the signal lines of the pixels. At this time, since the duty ratio ofthe sampling signal is smaller than that of the first clock signal, itbecomes possible to realize complete non-overlap sampling.

Particularly in the present invention, the clock generating means isdivided into an external clock generating circuit and an internal clockgenerating circuit. The external clock generating circuit supplies thesecond clock signal, while the internal clock generating circuitgenerates the first clock signal, whereby the number of clock signalsinputted externally to the panel can be reduced. Consequently, it isrendered possible to simplify the terminals, wiring, and so forth formedin the panel for external connection. The external clock generatingcircuit is capable of variably adjusting the pulse width of the secondclock signals. Meanwhile, the internal clock generating circuitgenerates the first clock signal having a fixed pulse width. For thepurpose of suppressing occurrence of vertical streaks and setting alarge ghost margin by complete non-overlap sampling, it is necessary toset the pulse width of the second clock signal to an optimal value. Inthis case, the configuration of the external clock generating circuitcan be designed relatively freely, so that the circuit is preferable forgenerating a clock signal of a variable pulse width. On the other hand,the first clock signal used for operating the horizontal driving circuitmay be fixed in its pulse width. Therefore, the configuration of theinternal clock generating circuit to generate the first clock signal maybe relatively simple, and accordingly it can be incorporated preferablyin the panel.

In order to achieve the second object of the present invention, thefollowing means have been contrived. The display device of the inventionincludes a panel having gate lines in rows, signal lines in columns,pixels arrayed to form a matrix in the intersections of such rows andcolumns, and n video lines for supplying video signals separated into nroutes (where n is an integer greater than two) in a predetermined phaserelationship; a vertical driving circuit connected to the gate lines andselecting the row of the pixels sequentially; a sampling switch groupdisposed correspondingly to each signal line and connected between the nvideo lines in units of n signal lines; a horizontal driving circuitoperating in accordance with a clock signal of a predetermined period,and sequentially generating sampling pulses, which are not overlappedwith respect to the switches of the sampling switch group connected tothe same video line but are overlapped with respect to the adjacentswitches, and driving the switches sequentially to thereby write thevideo signal sequentially in the pixels of the selected row; and a clockgenerating means for generating a first clock signal used as a referenceto the operation of the horizontal driving circuit, and also generatinga second clock signal longer in pulse width than the first clock signal.The horizontal driving circuit has a shift register for outputting shiftpulses sequentially from respective shift stages thereof by performing ashift operation synchronously with the first clock signal; and anextracting switch group for sequentially generating the sampling pulsesby extracting the second clock signal in response to the shift pulsesoutputted sequentially from the shift register.

Preferably, the clock generating means is divided into an external clockgenerating circuit disposed outside the panel and supplying the firstclock signal externally to the horizontal driving circuit, and aninternal clock generating circuit formed within the panel and supplyingthe second clock signal internally to the horizontal driving circuit. Inthis case, the internal clock generating circuit generates the secondclock signal by processing the first clock signal supplied from theexternal clock generating circuit. Concretely, the internal clockgenerating circuit includes a delay circuit for delaying the first clocksignal, and generates the second clock signal out of the first clocksignal prior to the delay process and the first clock signal posteriorto the delay process. In this case, the delay circuit is composed of aneven number of inverters connected in series. The internal clockgenerating circuit has a NOR circuit for generating the second clocksignal by NOR-combining the first clock signal prior to the delayprocess with the first clock signal posterior to the delay process.

According to the above structure that represents the display deviceadopting a divided sample-and-hold driving method, shift pulsesoutputted from a horizontal driving circuit are extracted in response tothe other clock signal, and sampling pulses are generated. Due tointroduction of such a clock drive method, complete non-overlap of thesampling pulses can be realized between the signal lines connectedalternately to the same video line, while overlap is kept in thesampling pulses between the mutually adjacent signal lines.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram showing the fundamental structure of a displaydevice related to the first aspect of the present invention;

FIG. 2 is a typical block diagram showing a reference example of adisplay device;

FIG. 3 is a typical block diagram showing another reference example of adisplay device;

FIG. 4 is a block diagram showing a concrete structural example of aninternal clock generating circuit incorporated in the display device ofFIG. 1;

FIG. 5 is a timing chart for explaining the operation of the internalclock generating circuit shown in FIG. 4;

FIG. 6 is a circuit diagram showing a structural example of an activematrix type liquid crystal display device based on a dot sequentialdriving system according to an embodiment of the present invention;

FIG. 7 is a timing chart showing the timing relationship betweenhorizontal clock pulses HCK, HCKX and clock pulses DCK1, DCK2;

FIG. 8 is a timing chart for explaining the operation of a clock drivetype horizontal driving circuit according to the embodiment of theinvention;

FIG. 9 is a timing chart during a video signal sampling operationperformed in the clock drive type horizontal driving circuit accordingto the embodiment;

FIG. 10 is a timing chart showing the phase relationship between a videosignal Video at sample-and-hold positions when S/H=0 to 5 and completenon-overlap sampling pulses Vhk−1, Vhk, and Vhk+1;

FIG. 11 is a timing chart showing the phase relationship between a videosignal Video when S/H=1 and complete non-overlap sampling pulses Vhk−1,Vhk, and Vhk+1, and also showing potential changes on a signal line;

FIG. 12 is a timing chart showing the phase relationship between a videosignal Video when S/H=5 and complete non-overlap sampling pulses Vhk−1,Vhk, and Vhk+1, and also showing potential changes on a signal line;

FIG. 13 is a block diagram showing a fundamental structure of a displaydevice related to the second aspect of the present invention;

FIG. 14 is a waveform chart for explaining the operation of the displaydevice shown in FIG. 13;

FIG. 15 is a block diagram showing a concrete structural example of thedisplay device shown in FIG. 13;

FIG. 16 is a block diagram showing a concrete structural example of aninternal clock generating circuit incorporated in the display device ofFIG. 15;

FIG. 17 is a timing chart for explaining the operation of the internalclock generating circuit shown in FIG. 16;

FIG. 18 is a circuit diagram showing a structural example of an activematrix type liquid crystal display device based on a dot sequentialdriving system according to an embodiment of the present invention;

FIG. 19 is a block diagram showing a structural example of aconventional clock drive type horizontal driving circuit;

FIG. 20 is a timing chart for explaining the operation of theconventional clock drive type horizontal driving circuit;

FIG. 21 is a timing chart during a video signal sampling operationperformed in the conventional clock drive type horizontal drivingcircuit;

FIG. 22 is a diagram showing a structure of a sampling switch group whena video signal is inputted in parallel through m routes;

FIG. 23 is a waveform chart showing a state where a pulse-shaped videosignal is rounded;

FIG. 24 is a timing chart showing the phase relationship between a videosignal Video at sample-and-hold positions when S/H=0 to 5 and completenon-overlap sampling pulses Vhk−1, Vhk, and Vhk+1;

FIG. 25 is a timing chart showing the phase relationship between a videosignal Video when S/H=1 and complete non-overlap sampling pulses Vhk−1,Vhk, and Vhk+1, and also showing potential changes on a signal line;

FIG. 26 is a diagram showing a state where a fore ghost is causedanteriorly in the horizontal scanning direction;

FIG. 27 is a timing chart showing the phase relationship between a videosignal Video when S/H=5 and complete non-overlap sampling pulses Vhk−1,Vhk, and Vhk+1, and also showing potential changes on a signal line;

FIG. 28 is a diagram showing a state where a back ghost is causedposteiorly in the horizontal scanning direction;

FIG. 29 is a block diagram showing an example of a conventional displaydevice;

FIG. 30 is a waveform chart for explaining the operation of theconventional display device shown in FIG. 29; and

FIG. 31 is another waveform chart for explaining the operation of theconventional display device shown in FIG. 29.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter an embodiment of the present invention will be described indetail with reference to the accompanying drawings. FIG. 1 is a typicalblock diagram showing the fundamental structure of a display devicerelated to the first aspect of the present invention. As shown, thisdisplay device is composed of a panel 33 where a pixel array 15, avertical driving circuit 16, a horizontal driving circuit 17, and soforth are formed integrally. The pixel array 15 includes gate lines 13in rows, signal lines 12 in columns, and pixels 11 arrayed to form amatrix in the intersections of such rows and columns. The verticaldriving circuit 16 is disposed separately on the left and right and isconnected to the two ends of each gate line 13 for selecting the row ofthe pixels 11 sequentially. The horizontal driving circuit 17 isconnected to the signal lines 12 and operates in accordance with a clocksignal of a predetermined period in a manner to write a video signalsequentially in the pixels 11 of the selected row. The display devicefurther has a clock generating means, which generates first clocksignals HCK and HCKX used as a reference to the operation of thehorizontal driving circuit 17, and second clock signals DCK1, DCK1X,DCK2, DCK2X being equal in period to but smaller in duty ratio than thefirst clock signals HCK and HCKX. HCKX is an inverted signal of HCK.Similarly, DCK1X is an inverted signal of DCK1, and DCK2X is an invertedsignal of DCK2. A precharge circuit 20 is connected to each signal line12 and executes precharge prior to writing the video signal so as toimprove the image quality.

A characteristic item of the present invention resides in that thehorizontal driving circuit 17 has a shift register, a first switch groupand a second switch group. The shift register performs a shift operationsynchronously with the first clock signals HCK, HCKX and outputs shiftpulses sequentially from the respective shift stages thereof. The firstswitch group extracts the second clock signals DCK1, DCK1X, DCK2, DCK2Xin response to the shift pulses outputted sequentially from the shiftregisters. The second switch group sequentially samples the videosignal, which is inputted externally, in response to the second clocksignals DCK1, DCK1X, DCK2, DCK2X and then supplies the sampled signal tothe signal lines 12. Due to such a structure, complete non-overlapsampling can be realized.

Another characteristic item of the present invention resides in that theaforementioned clock generating means is divided into an external clockgenerating circuit 18 and an internal clock generating circuit 19. Theexternal clock generating circuit 18 is provided on a driving systemboard (not shown) disposed outside the panel 33 and supplies the secondclock signals DCK1, DCK1X, DCK2, DCK2X externally to the panel 33.Meanwhile the internal clock generating circuit 19 is formed in thepanel 33 together with the vertical driving circuit 16 and thehorizontal driving circuit 17 and generates the first clock signals HCKand HCKX by processing the second clock signals DCK1, DCK1X, DCK2, DCK2Xsupplied from the external clock generating circuit 18. The first clocksignals HCK and HCKX generated internally are sent to the horizontaldriving circuit 17 together with the second clock signals DCK1, DCK1X,DCK2, and DCK2X. The external clock generating circuit 18 is capable ofvariably adjusting the duty ratios of the second clock signals DCK1,DCK1X, DCK2, DCK2X. In contrast therewith, the internal clock generatingcircuit 19 generates the first clock signals HCK and HCKX where the dutyratios are fixed.

FIG. 2 is a typical block diagram showing a reference example of adisplay device. In order to compare this example with the display deviceof the present invention, any component parts corresponding to those inFIG. 1 are denoted by like reference numerals. The point different fromthe display device of the invention shown in FIG. 1 is that the firstclock signals HCK, HCKX and the second clock signals DCK1, DCK1X, DCK2,DCK2X are supplied entirely from the external clock generating circuit18, and any internal clock generating circuit is not incorporated in thepanel 33. In the reference example of FIG. 2, at least six terminals andthe wirings related thereto are necessary for connecting the externalclock generating circuit 18 to the panel 33. In contrast therewith, thedisplay device of the present invention shown in FIG. 1 requires merelyfour terminals for external connection.

FIG. 3 is a typical block diagram showing another reference example of adisplay device. In order to compare this example with the display deviceof the present invention, any component parts corresponding to those inFIG. 1 are denoted by like reference numerals. The point different fromthe display device of the invention shown in FIG. 1 is that the firstclock signals HCK and HCKX are supplied externally from the externalclock generating circuit 18, while the second clock signals DCK1, DCK1X,DCK2, DCK2X are generated internally by the internal clock generatingcircuit 19. The internal clock generating circuit 19 logically processesthe first clock signals HCK and HCKX supplied thereto from the externalclock generating circuit 18 and forms the second clock signals DCK1,DCK1X, DCK2, DCK2X. The internal clock generating circuit 19 has arelatively simple logic circuit configuration, wherein inverters of apredetermined number of stages are employed for setting the pulse widthof the second clock signal DCK. That is, the first clock signal HCK isdelayed via the series-connected inverters to thereby set the pulsewidth of the second clock signal DCK. Since the pulse width of thesecond clock signal is determined by the number of stages of theconnected inverters, the pulse width is basically fixed and cannot bevariably adjusted. However, in the reference example of FIG. 3, only twoterminals for external connection are needed with regard to the firstclock signals HCK and HCKX.

In the reference example of FIG. 2, the second clock signal (hereinafterreferred to as DCK pulse in some case) is produced in a system boardoutside the panel, so that it is possible to freely adjust the phase andthe pulse width of the DCK pulse in relation to the first clock signal(hereinafter referred to as HCK pulse in some case). However, besidesthe first clock signals HCK and HCKX, four routes of input signals needto be added, i.e., the second clock signals DCK1, DCK1X, DCK2 and DCK2X,whereby four pad terminals are increased for external connection. Such anumerical increase of the pad terminals is not desirable since it bringsabout difficulty in reducing the panel size. Also in the referenceexample of FIG. 3, DCK pulses are produced in the panel on the basis ofthe HCK pulses supplied from the external clock generating circuit 18,so that the number of the pad terminals is not increased. However, asthe DCK pulse width is determined by the number of the inverters in theinternal clock generating circuit 19, it is impossible to attain freeadjustment of the DCK pulse width. Since an optimal DCK pulse widthneeds to be obtained with regard to a vertical streak or ghost margin,its variability is necessary. On the other hand, any increase of thenumber of pad terminals needs to be minimized. In view of suchrequirements, the display device of the present invention shown in FIG.1 is so contrived as to minimize the increase of the number of padterminals to two, i.e., from the known two terminals for HCK and HCKX tofour terminals for DCK1, DCK1X, DCK2 and DCK2X. Further, as the secondclock signals are supplied from the external clock generating circuit18, it becomes possible to optimally adjust the DCK pulse width.

FIG. 4 is a block diagram showing a concrete structure of the internalclock generating circuit 19 shown in FIG. 1. This internal clockgenerating circuit is formed at the upper right of the panel andproduces. HCK pulses out of the DCK pulses. As shown in the diagram, theinternal clock generating circuit fundamentally is composed of a D typeflip-flop. Particularly in this example, the D type flip-flop 50includes four NAND elements 51-54. The D type flip-flop 50 has an inputterminal D, a clock terminal CLK, and a pair of output terminals Q andQX. The D type flip-flop catches an input signal D by the leading edgeof a clock pulse CLK and produces its output signal Q. The other outputsignal QX is an inversion of one output signal Q. In this example, outof the second clock signals supplied from the external clock generatingcircuit, either DCK2X or DCK1 is used as the input signal. Also out ofthe second clock signals supplied from the external clock generatingcircuit, there is used a pulse waveform as a clock pulse CLK obtained byOR-processing DCK1 and DCK2 through an OR element 55 and then delayingits output in a delay circuit 60. The delay circuit 60 is composed ofinverters 61, 62, . . . 6 n connected in series.

FIG. 5 is a waveform chart for explaining the operation of the internalclock generating circuit shown in FIG. 4. The second clock signals DCK1and DCK1X supplied externally have a predetermined pulse width and aremutually opposite in polarity. Similarly, DCK2 and DCK2X have apredetermined pulse width and are mutually opposite in polarity. DCK1and DCK2 have a phase deviation of 180° C. from each other. In thisembodiment, clock pulses CLK are obtained by OR-processing DCK1 andDCK2. Since DCK1 and DCK2 have a phase deviation of 180° C. from eachother, the interval between the leading edges of the clock pulses CLK iscoincident with a ½ period of desired HCK pulses. The HCK pulses have aduty ratio of 50%, while the DCK pulses are equal in period to the HCKpulses and have a smaller duty ratio. In this embodiment, DCK2X is usedas an input signal D. Here, in order to avoid that the leading edge ofthe input pulse D and the leading edge of the clock pulse CLK overlapwith each other, CLK is delayed previously in the delay circuit 60 andthen is inputted to the D type flip-flop 50. As mentioned, the D typeflip-flop catches the input signal D by the leading edge of the clockpulse CLK and then sends the same to the output terminal Q. Therefore,the output signal Q is equal in period to the DCK pulse and has a dutyratio of 50% so as to be usable as an HCK pulse. At the output terminalQX, there is obtained HCKX, which is an inversion of the HCK pulse. TheHCK pulse thus obtained is used for the operation of the horizontaldriving circuit. The DCK pulses are supplied from an external clockgenerating circuit provided on a driving system board. The DCK pulsewidth is variable on the system board side. Thus, in the display deviceof the present invention, the DCK pulse width can be varied, and thenumber of the input signals supplied to the panel can be reduced tofour.

FIG. 6 is a circuit diagram showing a structural example of an activematrix type liquid crystal display device based on a dot sequentialdriving system according to an embodiment of the present invention whereliquid crystal cells for example are used as display elements(electro-optical elements) of pixels. For the purpose of simplifying thediagram, there is shown here an exemplary case of a pixel array withfour rows and four columns. In an active matrix type liquid crystaldisplay device, it is usual that a thin film transistor (TFT) is used asa switching element of each pixel.

In FIG. 6, each of the four-row four-column pixels 11 arrayed to form amatrix includes a thin film transistor TFT serving as a pixeltransistor, a liquid crystal cell LC where a pixel electrode isconnected to a drain electrode of the thin film transistor TFT, and ahold capacitance Cs of which one electrode is connected to the drainelectrode of the thin film transistor TFT. With respect to such pixels11, signal lines 12-1 to 12-4 are wired column by column in the pixelarray direction, and gate lines 13-1 to 13-4 are wired row by row in thepixel array direction.

In each of the pixels 11, the source electrode (or drain electrode) ofthe thin film transistor TFT is connected to the corresponding one ofthe signal lines 12-1 to 12-4. The gate electrode of the thin filmtransistor TFT is connected to the gate lines 13-1 to 13-4 respectively.The counter electrode of the liquid crystal cell LC and the otherelectrode of the hold capacitance Cs are connected to a Cs line 14 incommon between the pixels. A predetermined DC voltage is applied as acommon voltage Vcom to the Cs line 14.

Thus, there is structured a pixel array 15 where the pixels 11 arearrayed to form a matrix, and the signal lines 12-1 to 12-4 are wiredcolumn by column with respect to the pixels 11, and further the gatelines 13-1 to 13-4 are wired row by row. In this pixel array 15, one endof each of the gate lines 13-1 to 13-4 is connected to the output end ofthe corresponding row of a vertical driving circuit 16 disposed, forexample, on the left of the pixel array 15.

The vertical driving circuit 16 performs vertical scanning (in the rowdirection) per field and sequentially selects, row by row, the pixels 11connected to the gate lines 13-1 to 13-4. More specifically, when ascanning pulse Vg1 is delivered from the vertical driving circuit 16 tothe gate line 13-1, the pixels of the respective columns on the firstrow are selected. When a scanning pulse Vg2 is delivered to the gateline 13-2, the pixels of the respective columns on the second row areselected. Similarly, scanning pulses Vg3 and Vg4 are deliveredsequentially to the gate lines 13-3 and 13-4.

A horizontal driving circuit 17 is disposed, for example, above thepixel array 15. And an external clock generating circuit (timinggenerator) 18 is provided for supplying various clock signals to thevertical driving circuit 16 and the horizontal driving circuit 17. Thisexternal clock generating circuit 18 generates a vertical start pulseVST to instruct start of vertical scanning, vertical clock pulses VCKand VCKX having mutually opposite phases and used as a reference tovertical scanning, and a vertical start pulse HST to instruct start ofhorizontal scanning. In addition, the external clock generating circuit18 further generates clock pulses DCK1 and DCK2 used to produce samplingpulses therefrom.

An internal clock generating circuit 19 is provided separately from theexternal clock generating circuit 18. The internal clock generatingcircuit 19 generates, on the basis of DCK1 and DCK2 supplied from theexternal clock generating circuit 18, HCK and HCKX having mutuallyopposite phases and used as a reference to horizontal scanning. As shownin the timing chart of FIG. 7, the horizontal clock pulses HCK and HCKXhave a period T1, a pulse width t1, and a duty ratio of 50%. In contrasttherewith, the pulses DCK1 and DCK2 have a period T2 and a pulse widtht2. Since T1=T2, the pulses HCK and DCK are equal in period to eachother. On the other hand, t2 is smaller than t1, and the duty ratio ofthe pulse DCK is smaller than that of the pulse HCK. Here, the term“duty ratio” is defined as a ratio of the pulse width t to the pulserepetition period T in a pulse waveform.

In this embodiment, the duty ratio (t1/T1) of the horizontal clockpulses. HCK and HCKX is 50%, and the duty ratio (t2/T2) of the clockpulses DCK1 and DCK2 is smaller than 50%, i.e., the pulse width t2 ofthe clock pulses DCK1 and DCK2 is set to be narrower than the pulsewidth t1 of the horizontal clock pulses HCK and HCKX.

The horizontal driving circuit 17 sequentially samples the input videosignal Video per horizontal scanning interval (1H) and writes thesampled signal in the pixels 11 of the row selected by the verticaldriving circuit 16. In this embodiment, the horizontal driving circuit17 is formed by adopting a clock drive method and includes a shiftregister 21, a clock extracting switch group 22, and a sampling switchgroup 23.

The shift register 21 is composed of four shift stages (S/R) 21-1 to21-4 corresponding to the pixel columns (four columns in thisembodiment) of the pixel array 15. In response to a horizontal startpulse HST, the shift register 21 performs a shift operationsynchronously with the horizontal clock pulses HCK and HCKX havingmutually opposite phases. Consequently, as shown in a timing chart ofFIG. 8, shift pulses Vs1 to Vs4 having a pulse width equal to the periodof the horizontal clock pulses HCK and HCKX are outputted sequentiallyfrom the shift stages 21-1 to 21-4 of the shift register 21.

The clock extracting switch group 22 is composed of four switches 22-1to 22-4 corresponding to the pixel columns of the pixel array 15,wherein one end of each of such switches 22-1 to 22-4 is connectedalternately to clock lines 24-1 and 24-2 through which the clock pulsesDCK2 and DCK1 are transmitted from the external clock generating circuit18 via the internal clock generating circuit 19. That is, one end ofeach of the switches 22-1 and 22-3 is connected to the clock line 24-1,and one end of each of the switches 22-2 and 22-4 is connected to theclock line 24-2, respectively.

The switches 22-1 to 22-4 of the clock extracting switch group 22 aresupplied respectively with shift pulses Vs1 to Vs4 outputtedsequentially from the shift stages 21-1 to 21-4 of the shift register21. When the shift pulses Vs1 to Vs4 have been delivered from the shiftstages 21-1 to 21-4 of the shift register 21, the switches 22-1 to 22-4of the clock extracting switch group 22 are turned on sequentially inresponse to the shift pulses Vs1 to Vs4, thereby extracting the clockpulses DCK2 and DCK1 of mutually opposite phases alternately.

The sampling switch group 23 is composed of four switches 23-1 to 23-4corresponding to the pixel columns of the pixel array 15, wherein oneend of each of the switches 23-1 to 23-4 is connected to the video line25 to which the video signal Video is inputted. The switches 23-1 to23-4 of the sampling switch group 23 are supplied respectively with theclock pulses DCK2 and DCK1, which have been extracted by the switches22-1 to 22-4 of the clock extracting switch group 22, as sampling pulsesVh1 to Vh4.

When the sampling pulses Vh1 to Vh4 have been delivered from theswitches 22-1 to 22-4 of the clock extracting switch group 22, theswitches 23-1 to 23-4 of the sampling switch group 23 are turned onsequentially in response to the sampling pulses Vh1 to Vh4, therebysequentially sampling the video signal Video inputted via the video line25 and then supplies the sampled signal to the signal lines 12-1 to 12-4of the pixel array 15.

In the horizontal driving circuit 17 according to this embodiment of theabove-described structure, the shift pulses Vs1 to Vs4 outputtedsequentially from the shift register 21 are not used as sampling pulsesVh1 to Vh4, but a pair of clock pulses DCK2 and DCK1 are extractedalternately in synchronism with the sampling pulses Vh1 to Vh4, and suchclock pulses DCK2 and DCK1 are used directly as sampling pulses Vh1 toVh4, so that it becomes possible to suppress fluctuations of thesampling pulses Vh1 to Vh4. As a result, any ghost derived fromfluctuations of the sampling pulses Vh1 to Vh4 can be eliminated.

Further differing from the related art wherein the sampling pulses Vh1to Vh4 are obtained by extracting the horizontal clock pulses HCKX andHCK, which serve as a reference to the shift operation of the shiftregister 21, the horizontal driving circuit 17 of this embodiment is socontrived that clock pulses DCK2 and DCK1 being equal in period to butsmaller in duty ratio than the horizontal clock pulses HCKX and HCK aregenerated separately, and such clock pulses DCK2 and DCK1 are extractedto be used as sampling pulses Vh1 to Vh4. Consequently, the followingadvantages effects are attainable.

That is, in the process of transmission from extraction of the clockpulses DCK2 and DCK1 by the switches 22-1 to 22-4 of the clockextracting switch group 22 to delivery of such extracted pulses to theswitches 23-1 to 23-4 of the sampling switch group 23, even if thepulses are somewhat delayed due to the wiring resistance, parasiticcapacitance, or the like and the waveforms of the extracted clock pulsesDCK2 and DCK1 are rounded, complete non-overlap waveforms are obtainedbetween the extracted clock pulses DCK2, DCK1 and the preceding andfollowing pulses respectively, as obvious especially from a timing chartof FIG. 9.

By using the clock pulses DCK2 and DCK1 of such complete non-overlapwaveforms as sampling pulses Vh1 to Vh4, now with regard to the kthstage for example in the sampling switch group 23, the operation ofsampling the video signal Video by the sampling switch of the kth stagecan be finished without fail before the sampling switch of the k+1thstage is turned on.

Consequently, if a charge/discharge noise is superposed on the videoline 25 at the moment any of the switches 23-1 to 23-4 of the samplingswitch group 23 is turned on, as shown in FIG. 8, the sampling operationin the current stage (relevant stage immediately prior to the nextstage) is performed without fail before occurrence of a charge/dischargenoise by the next-stage switching, so that it becomes possible toprevent sampling of the charge/discharge noise. As a result, completenon-overlap sampling can be realized between the sampling pulses in thehorizontal driving, hence suppressing appearance of vertical streaksthat may otherwise be caused by overlap sampling.

Since complete non-overlap sampling can thus be realized, a greaterghost margin free from occurrence of any ghost is attainable incomparison with the known value in the related art. Hereinafter adetailed description will be given on this point. FIG. 10 shows thephase relationship between a video signal Video at sample-and-holdpositions when S/H=0 to 5 for example and complete non-overlap samplingpulses Vhk−1, Vhk, and Vhk+1.

First, there is considered one case of S/H=1. FIG. 11 shows the phaserelationship between the video signal Video when S/H=1 and the samplingpulses Vhk−1, Vhk, and Vhk+1, and also shows a potential change on thesignal line. In the case of S/H=1, the sampling pulse Vhk−1 in the k−1thstage does not overlap with the black signal portion (pulse portion) ofthe video signal Video. Accordingly, when the pulse-shaped video signalVideo has been sampled by the sampling pulse Vhk, the black signal iswritten merely in the kth-stage signal line alone, so that no ghost iscaused at an anterior position in the horizontal scanning direction.

Next, there is considered another case of S/H=5. FIG. 12 shows the phaserelationship between the video signal Video when S/H=5 and the samplingpulses Vhk−1, Vhk, and Vhk+1, and also shows a potential change on thesignal line. In the case of S/H=5, the video black signal overlaps withthe sampling pulse Vhk+1 of the k+1th stage. Consequently, the blacksignal is written in the signal line of the k+1th stage when thesampling switch is turned on, and then the potential level is lowered toreturn to the gray level. However, since the amount of overlap is great,the signal line potential fails to return completely to the gray level.Therefore, a ghost is caused at a posterior position in the horizontalscanning direction.

In any other case of S/H=1 to 4, as in the above-described case ofS/H=5, the video black signal overlaps with the sampling pulse Vhk+1 ofthe k+1th stage, and the black signal is written in the signal line whenthe sampling switch is turned on. However, since the amount of overlapis smaller and the written black level is lower in comparison with theabove case of S/H=5, the signal line potential returns completely downto the gray level. Consequently, no ghost is caused at a posteriorposition in the horizontal scanning direction.

As the sampling pulses Vhk−1, Vhk, and Vhk+1 thus overlap with oneanother, overlap sampling is performed in the related art. In comparisonwith such related art where the ghost margin is three in total inclusiveof S/H=2, 3, 4, the ghost margin attainable in this embodiment thatadopts the complete non-overlap sampling method increases to five intotal since two states inclusive of S/H=0, 1 are added to the knownstates of S/H=2, 3, 4, whereby the ghost margin can be raised.

Regarding the above embodiment, a description has been given on anexemplary case of applying the present invention to a liquid crystaldisplay device equipped with an analog interface driving circuit, whichsamples an input analog video signal and then drives the pixels dotsequentially. However, the invention is applicable also to a liquidcrystal display device equipped with a digital interface drivingcircuit, which latches an input digital video signal, then converts thelatched signal into an analog video signal and, after sampling theanalog video signal, drives the pixels dot sequentially.

Also in the above embodiment, a description has been given on an exampleof applying the invention to an active matrix type liquid crystaldisplay device where liquid crystal cells are used as display elements(electro-optical elements) in the pixels. However, the application ofthe invention is not limited to such a liquid crystal display devicealone, and it may be applicable generally to any of active matrix typedisplay devices based on a dot sequential driving system where a clockdrive method is adopted for its horizontal driving circuit, such as anactive matrix type EL display device employing electroluminescence (EL)elements as display elements in the pixels.

As for the dot sequential driving system, besides the conventional 1Hinverse driving system and dot inverse driving system known heretofore,there is a dot-line inverse driving system wherein video signals ofmutually inverse polarities are written simultaneously in the pixels oftwo rows spaced apart by an odd number of rows from each other betweenadjacent pixel columns, e.g., in the pixels of two upper and lower rows,in such a manner that, in the pixel array after writing of the videosignals, the polarities become the same in the mutually adjacent leftand right pixels but inverse in the upper and lower pixels.

FIG. 13 is a typical block diagram showing another embodiment of adisplay device related to the second aspect of the present invention. Asshown, this display device includes a panel having gate lines 13 inrows, signal lines 12 in columns, pixels 11 arrayed to form a matrix inthe intersections of such gate and signal lines, and two video lines 25and 26 for separately supplying video signals Video1 and Video2, whichhave a predetermined phase relationship and are divided into two routes.Although video signals of two routes are used in this embodiment, it isgenerally possible to use video signals of n routes having apredetermined phase relationship. In such a case, n video lines may beprovided, wherein n is an integer greater than two. This display devicefurther includes, in addition to the panel mentioned above, a verticaldriving circuit 16, a horizontal driving circuit 17, and a clockgenerating means 89. Preferably, the vertical driving circuit 16 and thehorizontal driving circuit 17 are incorporated in the panel. Further, asampling switch group 23 is also formed in the panel. Each switch of thesampling switch group 23 is disposed correspondingly to each signal line12 and is connected between the two video lines in units of two signallines. More specifically, the switch corresponding to the first signalline is connected to one video line 25, while the switch correspondingto the second signal line is connected to the other video line 26. Thus,the signal lines 12 are connected alternately to the two video lines 25and 26. In general, the sampling switch group 23 is connected betweenthe n video lines in units of n signal lines.

The vertical driving circuit 16 is connected to each gate line 13 andselects the pixels 11 row by row sequentially. The horizontal drivingcircuit 17 operates in accordance with a clock signal of a predeterminedperiod and sequentially generates sampling pulses A, B, C, D, . . . andso forth, which are not overlapped with respect to the switches of thesampling switch group 23 connected to the same video line but areoverlapped with respect to the adjacent switches, thereby driving theswitches in sequence to write the video signals Video1 and Video2sequentially in the pixels 11 of the selected row.

A characteristic item of the present invention resides in that the clockgenerating means 89 generates a first clock signal HCK used as areference to the operation of the horizontal driving circuit 17 and alsogenerates second clock signals DCK1 and DCK2 each having a pulse widthlonger than that of the first clock signal HCK. The horizontal drivingcircuit 17 is composed of a shift register 21 and an extracting switchgroup 22. Each stage of the shift register 21 is denoted by S/R here.The shift register 21 shifts the horizontal start pulse HSTsynchronously with the first clock signal HCK and outputs shift pulsesA, B, C, D, . . . and so forth sequentially from the respective shiftstages S/R. The start pulse HST is supplied from the clock generatingmeans 89. The respective switches of the extracting switch group 22extract the second clock signals DCK1 and DCK2 in response to the shiftpulses A, B, C, D, . . . and so forth outputted sequentially from theshift register 21 and produce the aforementioned sampling pulses A′, B′,C′, D′, . . . and so forth. In this manner, the horizontal drivingcircuit 17 sequentially generates sampling pulses, which are notoverlapped with respect to the switches of the sampling switch group 23connected to the same video line but are overlapped with respect to theadjacent switches, thereby driving the switches in sequence. Forexample, the sampling pulses A′ and B′ overlap with each other, whilethe pulses A′ and C′ do not overlap completely with each other.

Referring to FIG. 14, an explanation will be given on the operation ofthe display device shown in FIG. 13. The horizontal driving circuit 17operates in accordance with the first clock signal HCK (hereinafterreferred to as HCK pulse in some case) and generates shift pulses A, B,C, D by sequentially transferring the start pulse HST. The clockgenerating means 89 supplies, in addition to the HCK pulse, second clocksignals DCK1 and DCK2 (hereinafter referred to as DCK pulse in somecase) to the horizontal driving circuit 17. As obvious from the timingchart of FIG. 14, the DCK pulse is equal in period to but greater inpulse width than the HCK pulse. DCK1 and DCK2 have a phase deviation of180° C. from each other.

The horizontal driving circuit 17 shown in FIG. 13 turns on/off theextracting switch group 22 by the shift pulses A, B, C, D, . . . toextract DCK pulses, whereby sampling pulses A′, B′, C′, D′, . . . aregenerated. More specifically, a sampling pulse A′ is generated byextracting the DCK1 pulse in accordance with the shift pulse A.Similarly, a sampling pulse B′ is obtained by extracting the DCK2 pulsein accordance with the shift pulse B. Subsequently, sampling pulses C′,D′, . . . and so forth are obtained by extracting the DCK pulsessimilarly in accordance with the shift pulses. Due to introduction ofsuch a clock drive method, it is rendered possible to keep overlapbetween the mutually adjacent sampling pulses and to attain completenon-overlap between the alternate signal lines connected to the samevideo line. For example, the sampling pulses A′ and B′ overlap with eachother, while the pulses A′ and C′ do not overlap completely with eachother.

Such complete non-overlap can cope with vertical streaks or ghostspeculiar to the active matrix type display device based on a dotsequential driving system. In the example of FIG. 14, when the samplingpulse A′ has fallen for instance, the video signal Video1 is sampledproperly on the corresponding signal line, as indicated by a dotted-linearrow. Thereafter, when the sampling pulse C′ rises as indicated by asolid-line arrow, a charge/discharge is caused on the signal line, sothat the potential of the video signal Video1 is varied downward toconsequently superpose a noise. However, at the time point of occurrenceof this noise, no harmful effect is exerted since the sampling pulse A′has already fallen.

As described, in the present invention, there is introduced a clockdrive method that employs DCK pulses to execute divided sample-and-holddriving. In order to deal with the divided sample-and-hold driving, DCKpulses having a longer pulse width and a different duty ratio incomparison with the HCK pulses are used as those to be extracted by theclock drive. Since the DCK pulses are thus extracted by the shift pulsesoutputted from the respective stages of the shift register, the mutuallyadjacent sampling pulses are made to overlap with each other, while thesampling pulses corresponding to the same video line are made not tooverlap with each other. In this manner, it becomes possible toeliminate vertical streaks in a checkered pattern obtained by dot-lineinverse driving or in a specific pattern such as a one-dot horizontalline pattern obtained by dot-line inverse driving. It further becomespossible to simultaneously solve the problems of vertical streaks andghosts peculiar to the dot-sequential active matrix display device.

FIG. 15 is a typical block diagram showing a concrete structural exampleof the display device according to the present invention. As shown, thisdisplay device is composed of a panel 33 where a pixel array 15, avertical driving circuit 16, a horizontal driving circuit 17, and soforth are formed integrally. The pixel array 15 includes gate lines 13in rows, signal lines 12 in columns, and pixels 11 arrayed to form amatrix in the intersections of such gate and signal lines. The verticaldriving circuit 16 is disposed separately on the left and right and isconnected to the two ends of each gate line 13 for selecting the row ofthe pixels 11 sequentially. The horizontal driving circuit 17 isconnected to the signal lines 12 and operates in accordance with HCKpulses of a predetermined period in a manner to write a video signalsequentially in the pixels 11 of the selected row. This display devicefurther has a clock generating means, which generates HCK pulses servingas a reference to the operation of the horizontal driving circuit 17 andalso generates DCK pulses equal in period to but greater in pulse widththan the HCK pulses. The HCK pulses include the clock signals HCK andHCKX. HCKX is an inverted signal of HCK. The DCK pulses include clocksignals DCK1, DCK1X, DCK2, and DCK2X. DCK1X is an inverted signal ofDCK1, and DCK2X is an inverted signal of DCK2. DCK1 and DCK2 have aphase deviation of 180° C. from each other. For the purpose ofsimplifying the diagram, video lines and a sampling switch groupincorporated actually in the panel 33 are omitted here. Further, aprecharge circuit 20 is connected to each signal line 12 and, prior tosampling the video signal from the horizontal driving circuit 17,applies a potential of a predetermined level to each signal line 12previously to thereby improve the display definition.

A characteristic item of the this embodiment resides in that the clockgenerating means is divided into an external clock generating circuit 18and an internal clock generating circuit 19. The external clockgenerating circuit 18 is provided on a driving system board (not shown)disposed outside the panel 33 and supplies the first clock signals HCKand HCKX externally to the internal horizontal driving circuit 17.Meanwhile the internal clock generating circuit 19 is formed in thepanel 33 together with the vertical driving circuit 16 and thehorizontal driving circuit 17. The circuit 19 generates the second clocksignals DCK1, DCK1X, DCK2, and DCK2X internally and then supplies thesesignals to the horizontal driving circuit 17. The internal clockgenerating circuit 19 generates DCK pulses by processing the HCK pulsessupplied thereto from the external clock generating circuit 18. Anincrease of the number of input pads formed in the panel 33 can beprevented by producing the DCK pulses within the panel. Assuming thatthe entire HCK and DCK pulses are supplied externally, a total of sixinput pads are required. In this embodiment, four input pads can becurtailed by producing the DCK pulses within the panel.

FIG. 16 is a block diagram showing a concrete structural example of theinternal clock generating circuit 19 shown in FIG. 15. Viewing now thefirst route (1), the first clock signal HCK supplied from the externalclock generating circuit is divided into two. One is supplied directlyto one input terminal of a NOR circuit 55 a, while the other is suppliedto a delay circuit composed of four inverters 51 a to 54 a connected inseries. The output of the delay circuit is supplied to the other inputterminal of the NOR circuit 55 a. In this manner, the non-delayed signalHCK and the delayed signal HCK′ are NOR-processed in the NOR circuit 55a. The signal outputted from the NOR circuit 55 a is inverted by aninverter 56 and then is outputted as a clock signal DCK1 via a buffer57. The signal obtained from the output terminal of the NOR circuit 55 ais branched and outputted via a buffer 58 as DCK1X, which is then sentto the horizontal driving circuit. It is generally known that a pulsesignal delays whenever passing through an inverter. In this embodiment,therefore, the clock signal HCK′ having passed through a plurality ofinverters delays by several tens of nanoseconds in comparison with theclock signal HCK having not passed through any inverter. These two clocksignals HCK and HCK′ are NOR-processed to consequently produce desiredclock signals DCK1 and DCK1X each being greater in pulse width than thesignal HCK. Similarly to the above, DCK2 and DCK2X are generated in theroute (2).

FIG. 17 is a waveform chart for explaining the operation of the internalclock generating circuit shown in FIG. 16. In FIG. 17, (1) representsthe operation of the first route (1) shown in FIG. 16, and (2)represents the operation of the second route (2) shown in FIG. 16.Viewing FIG. 17 (1) now, HCK′ has a delay of a predetermined time ascompared with HCK. This delay amount is optimally settable by the numberof stages of the series-connected inverters. A signal DCK1X having anextended pulse width can be obtained by NOR-processing the pulses HCKand HCK′, which are deviated mutually in phase through the delayprocess. A signal DCK1 is obtained by inverting DCK1X by means of theoutput inverter. Similarly, as shown in FIG. 17 (2), a signal DCK2 isobtained through mutual logical processing of the non-delayed signalHCKX and the delayed signal HCKX′. A signal DCK2X is obtained byinverting the signal DCK2.

FIG. 18 is a circuit diagram showing a structural example of an activematrix type liquid crystal display device based on a dot sequentialdriving system according to an embodiment of the present invention whereliquid crystal cells for example are used as display elements(electro-optical elements) of pixels. For the purpose of simplifying thediagram, there is shown here an exemplary case of a pixel array withfour rows and four columns. In an active matrix type liquid crystaldisplay device, it is usual that a thin film transistor (TFT) is used asa switching element of each pixel.

In FIG. 18, each of the four-row four-column pixels 11 arrayed to form amatrix includes a thin film transistor TFT serving as a pixel transistora liquid crystal cell LC where a pixel electrode is connected to a drainelectrode of the thin film transistor TFT, and a hold capacitance Cs ofwhich one electrode is connected to the drain electrode of the thin filmtransistor TFT. With respect to such pixels 11, signal lines 12-1 to12-4 are wired column by column in the pixel array direction, and gatelines 13-1 to 13-4 are wired row by row in the pixel array direction.

In each of the pixels 11, the source electrode (or drain electrode) ofthe thin film transistor TFT is connected the corresponding one of thesignal lines 12-1 to 12-4. The gate electrode of the thin filmtransistor TFT is connected to the gate lines 13-1 to 13-4 respectively.The counter electrode of the liquid crystal cell LC and the otherelectrode of the hold capacitance Cs are connected to a Cs line 14 incommon between the pixels. A predetermined DC voltage is applied as acommon voltage Vcom to the Cs line 14.

Thus, there is structured a pixel array 15 where the pixels 11 arearrayed to form a matrix, the signal lines 12-1 to 12-4 are wired columnby column with respect to the pixels 11, and the gate lines 13-1 to 13-4are wired row by row. In this pixel array 15, one end of each of thegate lines 13-1 to 13-4 is connected to the output terminal of thecorresponding stage of a vertical driving circuit 16 disposed, forexample, on the left of the pixel array 15.

The vertical driving circuit 16 performs vertical scanning (in the rowdirection) per field and sequentially selects, row by row, the pixels 11connected to the gate lines 13-1 to 13-4. More specifically, when ascanning pulse Vg1 is delivered from the vertical driving circuit 16 tothe gate line 13-1, the pixels of the respective columns on the firstrow are selected. When a scanning pulse Vg2 is delivered to the gateline 13-2, the pixels of the respective columns on the second row areselected. Similarly, scanning pulses Vg3 and Vg4 are deliveredsequentially to the gate lines 13-3 and 13-4.

A horizontal driving circuit 17 is disposed, for example, above thepixel array 15. And an external clock generating circuit (timinggenerator) 18 is provided for supplying various clock signals to thevertical driving circuit 16 and the horizontal driving circuit 17. Thisexternal clock generating circuit 18 generates a vertical start pulseVST to instruct start of vertical scanning, vertical clock pulses VCKand VCKX having mutually opposite phases and used as a reference tovertical scanning, a vertical start pulse HST to instruct start ofhorizontal scanning, and horizontal clock pulses HCK and HCKX ofmutually opposite phases serving as a reference to the horizontalscanning.

An internal clock generating circuit 19 is provided separately from theexternal clock generating circuit 18. The internal clock generatingcircuit 19 generates pairs of clock pulses DCK1 and DCK2, which areequal in period to but greater in pulse width than the horizontal clockpulses HCK and HCKX.

The horizontal driving circuit 17 sequentially samples video signalsVideo1 and Video2, which are inputted from two video lines 25 and 26,per horizontal scanning interval (1H), and writes the sampled signals inthe pixels 11 of the row selected by the vertical driving circuit 16. Inthis embodiment, the horizontal driving circuit 17 is formed by adoptinga clock drive method and includes a shift register 21, a clockextracting switch group 22, and a sampling switch group 23.

The shift register 21 is composed of four shift stages (S/R) 21-1 to21-4 corresponding to the pixel columns (four columns in thisembodiment) of the pixel array 15. In response to a horizontal startpulse HST, the shift register 21 performs a shift operationsynchronously with the horizontal clock pulses HCK and HCKX havingmutually opposite phases. Consequently, shift pulses A to D having apulse width equal to the period of the horizontal clock pulses HCK andHCKX are outputted sequentially from the shift stages 21-1 to 21-4 ofthe shift register 21.

The clock extracting switch group 22 is composed of four switches 22-1to 22-4 corresponding to the pixel columns of the pixel array 15,wherein one end of each of such switches 22-1 to 22-4 is connectedalternately to clock lines 24-1 and 24-2 through which the clock pulsesDCK2 and DCK1 are transmitted from the internal clock generating circuit19. That is, one end of each of the switches 22-1 and 22-3 is connectedto the clock line 24-1, and one end of each of the switches 22-2 and22-4 is connected to the clock line 24-2, respectively.

The switches 22-1 to 22-4 of the clock extracting switch group 22 aresupplied respectively with shift pulses A to D outputted sequentiallyfrom the shift stages 21-1 to 21-4 of the shift register 21. When theshift pulses A to D have been delivered from the shift stages 21-1 to21-4 of the shift register 21, the switches 22-1 to 22-4 of the clockextracting switch group 22 are turned on sequentially in response to theshift pulses A to D, thereby extracting the clock pulses DCK2 and DCK1of mutually opposite phases alternately.

The sampling switch group 23 is composed of four switches 23-1 to 23-4corresponding to the pixel columns of the pixel array 15, wherein oneend of each of the switches 23-1 to 23-4 is connected alternately to thevideo line 25 for inputting the video signal Video1 and to the videoline 26 for inputting the video signal Video2. The switches 23-1 to 23-4of the sampling switch group 23 are supplied respectively with the clockpulses DCK2 and DCK1, which have been extracted by the switches 22-1 to22-4 of the clock extracting switch group 22, as sampling pulses A′ toD′.

When the sampling pulses A′ to D′ have been delivered from the switches22-1 to 22-4 of the clock extracting switch group 22, the switches 23-1to 23-4 of the sampling switch group 23 are turned on sequentially inresponse to the sampling pulses A′ to D′, thereby sequentially andalternately sampling the video signals Video1 and Video2 inputted viathe video line 25 and 26, and then supplies the sampled signals to thesignal lines 12-1 to 12-4 of the pixel array 15.

In the horizontal driving circuit 17 according to this embodiment of theabove-described structure, the shift pulses A to b outputtedsequentially from the shift register 21 are not used directly assampling pulses A′ to D′, but a pair of clock pulses DCK2 and DCK1 areextracted alternately in synchronism with the shift pulses A to D, andsuch clock pulses DCK2 and DCK1 are used as sampling pulses A′ to D′.Therefore, it becomes possible to suppress fluctuations of the samplingpulses A′ to D′. As a result, any ghost derived from fluctuations of thesampling pulses A′ to D′ can be eliminated.

INDUSTRIAL AVAILABILITY

As described hereinabove, according to the first aspect of the presentinvention in an active matrix type display device based on a dotsequential driving system, there is employed, in horizontal drivingperformed by a clock drive method, a second clock signal, which is equalin period to but smaller in duty ratio than a first clock signal servingas a reference to horizontal scanning, and such second clock signal isextracted and used as a sampling pulse to sample a video signal, so thatcomplete non-overlap sampling can be realized to consequently suppressoccurrence of vertical streaks that may otherwise be caused by overlapsampling, and further the ghost margin can be raised. Particularlyaccording to the present invention, the first clock signal is producedinternally by processing the second clock signal supplied externally.Therefore, it becomes possible to minimize an increase in the number ofterminals and the number of wirings to be formed in the panel. Moreover,since the second clock signal is supplied externally, the pulse widththereof is freely adjustable to an optimal value. Consequently, anoptimal DCK pulse width can be obtained with regard to any qualitydeterioration derived from vertical steaks and also to the ghost marginas well.

According to the second aspect of the present invention, clock drive isperformed by the use of DCK pulses, which are longer in pulse width thanand are different in duty ratio from the HCK pulses serving as areference to the operation of the horizontal driving circuit. As aresult, complete non-overlap sampling that complies with dividedsample-and-hold driving can be achieved to eventually suppressoccurrence of any vertical streak or ghost. And simultaneously, samplingpulses assigned to mutually adjacent signal lines in the dividedsample-and-hold driving are overlapped with each other, hence realizingelimination of vertical streaks, which may appear at the time ofdisplaying a dot checkered pattern in a line inverse driving mode or aone-dot horizontal line pattern in a dot-line inverse driving mode. Inaddition, the DCK pulses can be produced within the panel on the basisof the HCK pulses supplied externally, thereby preventing an increase inthe number of input pads or in the number of input wirings.

1. A display device comprising: a panel having gate lines in rows,signal lines in columns, and pixels arrayed to form a matrix in theintersections of such rows and columns; a vertical driving circuitconnected to said gate lines and selecting the row of the pixelssequentially; a horizontal driving circuit connected to said signallines and, in response to a clock signal of a predetermined period,writing a video signal sequentially in the pixels of the selected row;and a clock generating means for generating a first clock signal used asa reference to the operation of said horizontal driving circuit, andalso generating a second clock signal equal in period to but smaller induty ratio than the first clock signal; wherein said horizontal drivingcircuit has a shift register for outputting shift pulses sequentiallyfrom respective shift stages thereof by performing a shift operationsynchronously with the first clock signal; a first switch group forextracting the second clock signal in response to the shift pulsesoutputted sequentially from said shift register; and a second switchgroup for sampling the input video signal sequentially in response tothe second clock signal extracted by the switches of said first switchgroup, and supplying the sampled signal to each signal line; and saidclock generating means is divided into an external clock generatingcircuit disposed outside the panel and supplying the second clock signalexternally, and an internal clock generating circuit formed within thepanel and supplying the first clock signal to said horizontal drivingcircuit in accordance with the second clock signal.
 2. The displaydevice according to claim 1, wherein said internal clock generatingcircuit includes a D type flip-flop for generating the first clocksignal by processing the second clock signal supplied thereto from saidexternal clock generating circuit.
 3. The display device according toclaim 2, wherein said D type flip-flop is composed of a plurality ofNAND elements.
 4. The display device according to claim 1, wherein saidexternal clock generating circuit is capable of variably adjusting theduty ratio of the second clock signal.
 5. (Canceled)
 6. A display devicecomprising: a panel having gate lines in rows, signal lines in columnspixels arrayed to form a matrix in the intersections of such rows andcolumns, and n video lines for supplying video signals separated into nroutes (where n is an integer greater than two) in a predetermined phaserelationship; a vertical driving circuit connected to said gate linesand selecting the row of the pixels sequentially; a sampling switchgroup disposed correspondingly to each signal line and connected betweenthe n video lines in units of n signal lines; a horizontal drivingcircuit operating in accordance with a clock signal of a predeterminedperiod, and sequentially generating sampling pulses, which are notoverlapped with respect to the switches of said sampling switch groupconnected to the same video line but are overlapped with respect to theadjacent switches, and driving the switches sequentially to therebywrite the video signal sequentially in the pixels of the selected row;and a clock generating means for generating a first clock signal used asa reference to the operation of said horizontal driving circuit, andalso generating a second clock signal longer in pulse width than thefirst clock signal; wherein said horizontal driving circuit has a shiftregister for outputting shift pulses sequentially from respective shiftstages thereof by performing a shift operation synchronously with thefirst clock signal; and an extracting switch group for sequentiallygenerating the sampling pulses by extracting the second clock signal inresponse to the shift pulses outputted sequentially from said shiftregister, and said clock generating means is divided into an externalclock generating circuit disposed outside the panel and supplying thefirst clock signal externally to said horizontal driving circuit, and aninternal clock generating circuit formed within the panel and supplyingthe second clock signal internally to said horizontal driving circuit.7. The display device according to claim 6, wherein said internal clockgenerating circuit generates the second clock signal by processing thefirst clock signal supplied from said external clock generating circuit.8. The display device according to claim 7, wherein said internal clockgenerating circuit includes a delay circuit for delaying the first clocksignal, and generates the second clock signal out of the first clocksignal prior to the delay process and the first clock signal posteriorto the delay process.
 9. The display device according to claim 8,wherein said delay circuit is composed of an even number of invertersconnected in series.
 10. The display device according to claim 9,wherein said internal clock generating circuit has a NOR circuit forgenerating the second clock signal by NOR-combining the first clocksignal prior to the delay process with the first clock signal posteriorto the delay process.